There is difficulty in maintaining performance improvements in devices of deeply submicron generations. One general approach for improving performance is to try to increase carrier (electron and/or hole) mobilities. A promising avenue toward better carrier mobility is to apply tensile or compressive stress in the semiconductor channel regions. However, applying stress to non-planar, three dimensional (3D) FETs, such as a FinFET, or Tri-Gate device, may be more difficult. Stress liners commonly used for planar devices are not very efficient, partly because of the 3D nature of the device, and partly because of the shrinking of the device pitch as technology progresses. Smaller device pitch leads to thinner stress liners, and that results in less channel stress. One way to increase the stress coupling in e.g. FinFETs maybe to recess, namely etch down, the source/drain area of the fins or to epitaxially grow material from the fins within source/drain regions.
In some semiconductor devices, gate pairs may be separated by a narrow pitch and other gate pairs may be separated by a wider pitch. Currently, during epitaxy growth, it is difficult to manage the merging of epitaxial material grown from the fins within the source/drain regions separated by the wider pitch while also managing epitaxy overgrowth between fins separated by the narrow pitch. Further, epitaxy may grow at variable rates depending upon depending upon the location of the fin within a fin area of the structure. These epitaxy variations introduce subsequent problems when making and forming electrical contacts within these regions.